Experience with this development environment is required.Altera Quartus II v13.0 SP1 (Web Edition is also possible).
Altera quartus ii to program external flash drivers#
The software projects for the PCP and the host processor are split into drivers and apps: Note that hardware designs can be ported easily to other platforms by reusing the Qsys subsystem instances in hardware/ipcore/altera/qsys/mn_! Hardware/boards/terasic-de2-115/mn-single-hostif-gpio Host processor design with parallel host interface (application):.Hardware/boards/terasic-de2-115/mn-single-hostif-drv PCP design with parallel host interface (driver instance):.Hardware/boards/terasic-de2-115/mn-dual-hostif-gpio
PCP and host design within a single FPGA (driver and application):.The following MN FPGA designs are available for the TERASIC DE2-115 INK board: External (de-)multiplexed address-/data-bus.The two processors are connected by the Host Interface IP-Core, which supports the following interface implementations: Additionally, a hub IP-Core is provided enabling daisy chained networks. The Ethernet interface is built with the POWERLINK-optimized controller openMAC, which enables e.g.
The soft-core processor Altera Nios II is instantiated as PCP and also as host processor. The MN implementation uses the PCP (POWERLINK Communication Processor) and the host processor to execute the openPOWERLINK kernel and user layer. The POWERLINK MN on Altera FPGA implementation utilizes IP-Cores available in Altera Qsys and provided with the openPOWERLINK stack in the directory hardware/ipcore.